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d a t a sh eet preliminary speci?cation supersedes data of september 1994 file under integrated circuits, ic01 1995 dec 08 integrated circuits TDA1305t stereo 1fs data input up-sampling filter with bitstream continuous dual dac (bcc-dac2)
1995 dec 08 2 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t features easy application 16f s finite-duration impulse-response (fir) filter incorporated selectable system clock (f sys ) 256f s or 384f s i 2 s-bus serial input format (at f sys = 256f s ) or lsb fixed 16, 18 or 20 bits serial input mode (at f sys = 384f s ) slave-mode clock system cascaded 4-stage digital filter incorporating 2-stage fir filter, linear interpolator and sample-and-hold smoothed transitions before and after muting (soft mute) digital de-emphasis filter for three sampling rates of 32 khz, 44.1 khz and 48 khz 12 db attenuation via the attenuation input control double speed mode 2nd order noise shaper 96 (f sys = 384f s ) or 128 (f sys = 256f s ) times oversampling in normal speed mode 48 (f sys = 384f s ) or 64 (f sys = 256f s ) times oversampling in double speed mode bitstream continuous calibration concept small outline so28 package voltage output 1.5 v (rms) at line drive level low total harmonic distortion no zero crossing distortion inherently monotonic no analog post filtering required superior signal-to-noise ratio wide dynamic range (18-bit) single rail supply (3.4 to 5.5 v). general description the TDA1305t is a new generation of filter-dac which features a unique combination of bitstream and continuous calibration techniques. the converter functions as a bitstream converter for low signals while large signals are generated using the dynamic continuous calibration technique, thus resulting in low power consumption, small chip size and easy application. the TDA1305t is a dual cmos dac with up-sampling filter and noise shaper. the combination of high oversampling up to 16f s , 2nd order noise shaping and continuous calibration conversion ensures that only simple 1st order analog post filtering is required. the TDA1305t supports the i 2 s-bus data input mode with word lengths of up to 20 bits (at f sys = 256f s ) and the lsb fixed serial data input format with word lengths of 16, 18 and 20 bits (at f sys = 384f s ). four cascaded fir filters increase the oversampling rate to 16 times. a sample-and-hold function increases the oversampling rate to 96 times (f sys = 384f s ) or 128 times (f sys = 256f s ). a 2nd order noise shaper converts this oversampled data to a bitstream for the 5-bit dacs. the dacs are of the continuous calibration type and incorporate a special date coding. this ensures an extremely high signal-to-noise ratio, superior dynamic range and immunity to process variation and component ageing. two on-board operational amplifiers convert the digital-to-analog current to an output voltage. externally connected capacitors perform the required 1st order filtering so that no further post filtering is required. the unique combination of bitstream and continuous calibration techniques, together with a high degree of analog and digital integration, results in a single filter-dac with 18-bit dynamic range, high linearity and simple low cost application. ordering information type number package name description version TDA1305t so28 plastic small outline package; 28 leads; body width 7.5 mm sot136-1
1995 dec 08 3 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t quick reference data note 1. all v dd and v ss pins must be connected to the same supply. symbol parameter conditions min. typ. max. unit v ddd digital supply voltage note 1 3.4 5.0 5.5 v v dda analog supply voltage note 1 3.4 5.0 5.5 v v ddo operational ampli?er supply voltage note 1 3.4 5.0 5.5 v i ddd digital supply current v ddd =5v; at code 00000h - 30 - ma i dda analog supply current v dda =5v; at code 00000h - 5.5 8 ma i ddo operating ampli?er supply current v ddo =5v; at code 00000h - 6.5 9 ma v fs(rms) full-scale output voltage (rms value) v ddd =v dda =v ddo = 5 v 1.425 1.5 1.575 v (thd + n)/s total harmonic distortion plus noise-to-signal ratio at 0 db signal level -- 90 - 81 db - 0.003 0.009 % at - 60 db signal level -- 44 - 40 db - 0.63 0.1 % at - 60 db signal level; a-weighted -- 46 - db - 0.5 - % s/n signal-to-noise ratio at bipolar zero a-weighting; at code 00000h 100 108 - db br ns input bit rate at data input f s = 48 khz; normal speed -- 3.072 mbits br ds input bit rate at data input f s = 48 khz; double speed -- 6.144 mbits f sys system clock frequency 6.4 - 18.432 mhz tc fs full scale temperature coef?cient at analog outputs (vol and vor) - 100 10 - 6 - t amb operating ambient temperature - 30 - +85 c
1995 dec 08 4 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t block diagram fig.1 block diagram.
1995 dec 08 5 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t pinning symbol pin description v dda 1 analog supply voltage v ssa 2 analog ground test1 3 test input; pin should be connected to ground (internal pull-down resistor) bck 4 bit clock input ws 5 word select input data 6 data input clks1 7 clock selection 1 input clks2 8 clock selection 2 input v ssd 9 digital ground v ddd 10 digital supply voltage test2 11 test input; pin should be connected to ground (internal pull-down resistor) sysclki 12 system clock input n.c. 13 not connected (this pin should be left open-circuit) n.c. 14 not connected (this pin should be left open-circuit) v ssd 15 digital ground sysclko 16 system clock output deem1 17 de-emphasis on/off; f deem 32 khz, 44 khz and 48 khz deem2 18 de-emphasis on/off; f deem 32 khz, 44 khz and 48 khz musb 19 mute input (active low) dsmb 20 double-speed mode input (active low) a tsb 21 12 db attenuation input (active low) vol 22 left channel output filtcl 23 capacitor for left channel 1st order ?lter function should be connected between pins 22 and 23 filtcr 24 capacitor for right channel 1st order ?lter function should be connected between pins 25 and 24 vor 25 right channel output v ref 26 internal reference voltage for output channels (0.5v dd ) v sso 27 operational ampli?er ground v ddo 28 operational ampli?er supply voltage fig.2 pin configuration.
1995 dec 08 6 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t functional description the TDA1305t cmos digital-to-analog bitstream converter incorporates an up-sampling filter and noise shaper which increase the oversampling rate of 1f s input data to 96f s (f sys = 192f s ) or 128f s (f sys = 256f s ) in the normal speed mode. in the double speed mode the oversample rate of 1f s input data is increased to 48f s (f sys = 384f s ) or 64f s (f sys = 256f s ). this oversampling, together with the 5-bit dac, enables the filtering required for waveform smoothing and out-of-band noise reduction to be achieved by simple 1st order analog post filtering. system clock and data input format the TDA1305t accommodates slave mode only, this means that in all applications the system devices must provide a system clock of 256 or 384f s (f s = 32, 44.1 or 48 khz). the system frequency is selectable by means of pin clks1 and pin clks2. the sysclko output (pin 16) provides the system clock for external use. the TDA1305t supports the following data input modes: i 2 s-bus with data word lengths of up to 20 bits (at f sys = 256f s ). lsb fixed serial format with data word lengths of 16, 18 and 20 bits (at f sys = 384f s ). as this format idles on the msb it is necessary to know how many bits are being transmitted. the input format is shown in fig.3. left and right data-channel words are time-multiplexed. table 1 data input format and system clock. note 1. number of clock pulses within half an audio sample. test1 clks1 clks2 data input format system clock data clock (1) sysclko 000i 2 s up to 20 bits 256f s >20 256f s 0 0 1 lsb ?xed 16 bits 384f s 24 384f s 0 1 0 lsb ?xed 18 bits 384f s 24 384f s 0 1 1 lsb ?xed 20 bits 384f s 24 384f s 1 0 0 reserved --- 1 0 1 lsb ?xed 16 bits 384f s 32 384f s 1 1 0 lsb ?xed 18 bits 384f s 32 384f s 1 1 1 lsb ?xed 20 bits 384f s 32 384f s
1995 dec 08 7 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t fig.3 input formats.
1995 dec 08 8 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t mute soft mute is controlled by the musb at pin 9. when the input is active low the value of the samples is decreased smoothly to zero following a cosine curve. to step down the value of the data 32 coefficients are used, each one being used 31 times before stepping onto the next. when mute is released (pin 19 = high), the samples are returned to the full level again following a cosine curve with the same coefficients being used in the reverse order. mute is synchronized to prevent operation in the middle of a word. de-emphasis a digital de-emphasis is implemented for three sample rates (32, 44.1 and 48 khz). by selecting deem1 and deem2 de-emphasis can be applied by means of a fir filter. time constants of the de-emphasis are 50 m s and 15 m s. de-emphasis is synchronized to prevent operation in the middle of a word. the de-emphasis deviation from ideal 50 m s and 15 m s de-emphasis is given in table 4. table 2 de-emphasis. attenuation attenuation is controlled by the atsb input (pin 21). when the input is active low the sample is multiplied by a coefficient that provides 12 db attenuation. if the input is high the multiplication factor is 1. attenuation is synchronized to prevent operation in the middle of a word. double-speed mode double speed is controlled by the dsmb input (pin 20). when the input is active low the device operates in the double-speed mode. deem1 deem2 condition 0 0 de-emphasis disabled 0 1 de-emphasis for f s = 32 khz 1 0 de-emphasis for f s = 4.1 khz 1 1 de-emphasis for f s = 48 khz oversampling ?lter (normal-speed mode) in the normal-speed mode the oversampling filter consists of: a 91st order half-band low-pass fir filter which increases the oversampling rate from 1 time to 2 times. a 23rd order quarter band low-pass fir filter which increases the oversampling rate from 2 times to 8 times. a linear interpolation section which increases the oversampling rate to 16 times. this removes the spectral components around 8f s . a sample-and-hold section which provides another 6 times oversampling to 96 times. the zero-order hold characteristic of this sample-and-hold section plus the 1st order analog filtering remove the spectral components around 16f s . pass-band ripple and stop-band attenuation for normal-speed are given in table 3. oversampling ?lter (double-speed mode) in the double-speed mode the oversampling filter consists of: a 51st order half-band low-pass fir filter which increases the oversampling rate from 1 time to 2 times. a 7th order half-band low-pass fir filter which increases the oversampling rate from 2 times to 4 times. a linear interpolation section which increases the oversampling rate to 8 times. this removes the spectral components around 4f s . a sample-and-hold section which provides another 6 times oversampling to 48 times. the zero-order hold characteristic of this sample-and-hold section plus the 1st order analog filtering remove the spectral components around 8f s . pass-band ripple and stop-band attenuation for double-speed are given in table 3.
1995 dec 08 9 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t noise shaper in the normal speed mode the 2nd order digital noise shaper operates at 96f s (f sys = 384f s ) or 128f s (f sys = 256f s ). the digital noise shaper operates at 48f s (f sys = 384f s ) or 64f s (f sys = 256f s ) in double-speed mode. it shifts in-band quantization noise to frequencies well above the audio band. this noise shaping technique used in combination with a special data coding enables extremely high signal-to-noise ratios to be achieved. the noise shaper outputs a 5-bit pulse duration modulation (pdm) bitstream signal to the dac. continuous calibration dac the dual 5-bit dac uses the continuous calibration technique. this method, based on charge storage, involves exact duplication of a single reference current source. in the TDA1305t, 32 such current sources plus 1 spare source are continuously calibrated. the spare source is included to allow continuous converter operation. the dac receives a 5-bit data bitstream from the noise shaper. this data is then converted so that only small currents are switched to the output during digital silence (input 00000h). using this technique extremely high signal-to-noise performance is achieved. operational ampli?ers high precision, low-noise amplifiers together with the internal conversion resistors r conv1 and r conv2 convert the converter output current to a voltage capable of driving a line output. this voltage is available at vol and vor (1.5 v rms typical). connecting external capacitors cext1 and cext2 between filtcl and vol and between filtcr and vor respectively provides the required 1st order post filtering for the left and right channels (see fig.1). the combinations of r conv1 with cext1 and r conv2 with cext2 determine the 1st order fall-off frequencies. internal reference circuitry internal reference circuitry ensures that the output voltage signal is proportional to the supply voltage, thereby maintaining maximum dynamic range for supply voltages from 3.4 to 5.5 v and making the circuit also suitable for battery-powered applications. limiting values in accordance with the absolute maximum rating system (iec 134). notes 1. human body model; c = 100 pf, r = 1500 w , v = 2000 v, 3 pulses positive and 3 pulses negative. 2. machine model; c = 200 pf, r = 10 w , l = 0.5 m h. thermal characteristics symbol parameter conditions min. max. unit v ddd digital supply voltage - 7.0 v v dda analog supply voltage - 7.0 v v ddo operational ampli?er supply voltage - 7.0 v t xtal maximum crystal temperature - +150 c t stg storage temperature - 65 +150 c t amb ambient operating temperature - 30 +85 c v es electrostatic handling note 1 - 2000 +2000 v note 2 - 200 +200 v symbol parameter value unit r th j-a thermal resistance from junction to ambient in free air 75 k/w
1995 dec 08 10 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t quality specification in accordance with snw-fq-611e . the number of this quality specification can be found in the quality reference handbook . the handbook can be ordered using the code 9398 510 63011. digital characteristics v dd = 3.4 to 5.5 v; v ss =0v; t amb = - 40 to +85 c; unless otherwise speci?ed. symbol parameter conditions min. typ. max. unit supply v ddd digital supply voltage note 1 3.4 5.0 5.5 v i ddd digital supply current v ddd =5v; at code 00000h - 30 40 ma v dda analog supply voltage note 1 3.4 5.0 5.5 v i dda analog supply current v dda =5v; at code 00000h - 5.5 8 ma v ddo operational ampli?er supply voltage note 1 3.4 5.0 5.5 v i ddo operational ampli?er supply current v ddo =5v; at code 00000h - 6.5 9 ma rr ripple rejection to v dda note 2 - 25 - db system clock input f sys system frequency f sys = 384f s 9.6 16.93 18.4 mhz f sys = 256f s 6.4 11.29 12.28 mhz v il low level input voltage note 3 - 0.5 - 0.2v dd v v ih high level input voltage note 3 0.8v dd - v dd + 0.5 v ? i li ? input leakage current note 4 -- 10 m a c i input capacitance -- 10 pf t cy clock cycle time f sys = 384f s 104 59.1 54.2 ns f sys = 256f s 156 88.6 81.3 ns digital inputs; ws, bck, data, dsmb, musb, deem1, deem2, a tsb, clks1, clks2, test1 and test2 v il low level input voltage note 3 - 0.5 - 0.3v dd v v ih high level input voltage note 3 0.7v dd - v dd + 0.5 v ? i li ? input leakage current note 4 -- 10 m a c i input capacitance -- 10 pf digital output; cdec v ol low level output voltage i ol = 0.4 ma 0 - 0.5 v v oh high level output voltage i oh = - 0.2 ma v dd - 0.5 - v dd v t r output rise time note 5 -- 20 ns t f output fall time note 5 -- 20 ns c l load capacitance -- 30 pf
1995 dec 08 11 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t notes 1. all v dd and v ss pins must be connected externally to the same supply. 2. v ripple = 1% of supply voltage; f ripple = 100 hz. ripple rejection rr to v dda is dependent on the value of the external capacitor (c ext3 in fig.1) connected to v ref . the value here assumes that c ext3 =1 m f. 3. minimum v il and maximum v ih are peak values to allow for transients. 4. i limni measured at v i = 0 v; i limax measured at v i = 5.5 v. 5. reference levels = 10% and 90%. analog characteristics v dd =v dda =v ddo =5v; v ss =0v; t amb =25 c; unless otherwise speci?ed. serial input data timing (see fig.4) f bck bit-clock input (data input rate) frequency f sys = 384f s - 48f s - mhz f sys = 256f s - 64f s - mhz f ws word select input frequency normal speed 25 44.1 48 khz double speed 50 88.2 96 khz t r rise time -- 20 ns t f fall time -- 20 ns t h bit clock time high 55 -- ns t l bit clock time low 55 -- ns t su data set-up time 40 -- ns t h data hold time 10 -- ns t suws word select set-up time 40 -- ns t hws word select hold time 10 -- ns symbol parameter conditions min. typ. max. unit reference values v ref reference voltage level 2.45 2.5 2.55 v r conv current-to-voltage conversion resistor 1.6 2.2 2.8 k w analog outputs res resolution -- 18 bit v fs(rms) full-scale output voltage (pins 23 and 25) (rms value) 1.425 1.5 1.575 v v off output voltage dc offset with respect to reference voltage level v ref - 80 - 65 - 50 mv tc fs full scale temperature coef?cient - 100 10 - 6 - symbol parameter conditions min. typ. max. unit
1995 dec 08 12 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t notes 1. measured with a 1 khz, 0 db, 18-bit sine wave generated at a sampling rate of 48 khz. the (thd + n)/s measured over a bandwidth of 20 hz to 20 khz. 2. measured with a 1 khz, -60 db, 18-bit sine wave generated at a sampling rate of 48 khz. the (thd + n)/s measured over a bandwidth of 20 hz to 20 khz. for 16-bit input signals, the performance is limited to the theoretical maximum. 3. measured with a 1 khz, -60 db, 18-bit sine wave generated at a sampling rate of 48 khz. the (thd + n)/s measured over a bandwidth of 20 hz to 20 khz and filtered with a a-weighted characteristic. for 16-bit input signals, the performance is limited to the theoretical maximum. 4. measured with a sine wave from 20 hz to 20 khz generated at a sampling rate of 48 khz. the (thd + n)/s measured over a bandwidth of 20 hz to 20 khz. test and application information filter characteristics (theoretical values) table 3 normal speed ?lter characteristics. (thd + n)/s total harmonic distortion plus noise-to-signal ratio at 0 db input level; note 1 -- 90 - 81 db - 0.003 0.009 % at - 60 db input level; note 2 -- 44 - 40 db - 0.63 1.0 % at - 60 db input level; a-weighted; note 3 -- 46 - db - 0.5 - % at 0 db input level; (20 hz to 20 khz); note 4 -- 90 - 81 db - 0.003 0.003 % s/n signal-to-noise ratio at bipolar zero a weighted; at code (00000h) 100 108 - db a cs channel separation 85 100 - db ?d v o ? unbalance between outputs - 0.2 0.3 db ? z o ? dynamic output impedance - 10 -w r l output load resistance 3 -- k w c l output load capacitance -- 200 pf item sample frequency range conditions characteristics pass band 44.1 khz 0 to 20 khz 0 0.025 db 32 khz 14.5 to 15 khz - 0.15 db (min.) stop band 44.1 khz 24.1 to 150 khz typical - 60 db (max.) worst case - 57 db (max.) 150 khz to in?nity typical - 57 db (max.) worst case - 47 db (max.) 32 khz 17 to 17.5 khz - 40 db (max.) symbol parameter conditions min. typ. max. unit
1995 dec 08 13 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t de-emphasis ?lter characteristics (theoretical values) table 4 de-emphasis deviation from ideal 50 m s to 15 m s de-emphasis network. double-speed characteristics table 5 double-speed ?lter characteristics. item sample frequency range characteristics gain deviation 44.1 and 48 khz 0 to 18 khz 0 0.05 db 18 to 20 khz 0.12 db (max.) 32 khz 0 to 13 khz 0 0.06 db 13 to 15 khz 0.22 db (max.) phase deviation 44.1 and 48 khz 0 to 15 khz 10 deg (max.) 15 to 20 khz 15 deg (max.) 32 khz 0 to 9 khz 10 deg (max.) 9 to 15 khz 16 deg (max.) item range conditions characteristics pass band 0 to 17 khz 0 0.075 db 17 to 20 khz - 0.3 db (min.) stop band 24.1 to 150 khz typical - 47 db (max.) worst case - 45 db (max.) 150 khz to in?nite typical - 33 db (max.) worst case - 25 db (max.) fig.4 timing of input signals.
1995 dec 08 14 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t application information fig.5 application diagram.
1995 dec 08 15 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t a typical application diagram is illustrated in fig.5. the left and right channel outputs can drive a line output directly. the series inductor (l) in the digital supply line, though not strictly necessary, helps to reduce crosstalk between the digital and analog circuits. in fig.6 measurements were taken with an 18-bit sine wave generated at a sampling rate of 48 khz. the (thd + n)/s was measured over a bandwidth of 20 hz to 20 khz. the graph was constructed from average measurement values of a small amount of engineering samples. no guarantee for typical values is implied. in fig.6 measurements were taken with an 18-bit sine wave generated at a sampling rate of 48 khz. the (thd + n)/s was measured over a bandwidth of 20 hz to 20 khz and filtered with a-weighted characteristics. the graph was constructed from average measurement values of a small amount of engineering samples. no guarantee for typical values is implied. fig.6 total harmonic distortion as a function of signal frequency. (1) level = - 60 db. (2) level = 0 db.
1995 dec 08 16 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t fig.7 total harmonic distortion as a function of signal level; (a-weighted).
1995 dec 08 17 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t package outline unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p q z y w v q references outline version european projection issue date iec jedec eiaj mm inches 2.65 0.30 0.10 2.45 2.25 0.49 0.36 0.32 0.23 18.1 17.7 7.6 7.4 1.27 10.65 10.00 1.1 1.0 0.9 0.4 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 1.1 0.4 sot136-1 x 14 28 w m q a a 1 a 2 b p d h e l p q detail x e z c l v m a e 15 1 (a ) 3 a y 0.25 075e06 ms-013ae pin 1 index 0.10 0.012 0.004 0.096 0.089 0.019 0.014 0.013 0.009 0.71 0.69 0.30 0.29 0.050 1.4 0.055 0.419 0.394 0.043 0.039 0.035 0.016 0.01 0.25 0.01 0.004 0.043 0.016 0.01 0 5 10 mm scale so28: plastic small outline package; 28 leads; body width 7.5 mm sot136-1 95-01-24 97-05-22
1995 dec 08 18 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t soldering introduction there is no soldering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. however, wave soldering is not always suitable for surface mounted ics, or for printed-circuits with high population densities. in these situations reflow soldering is often used. this text gives a very brief insight to a complex technology. a more in-depth account of soldering ics can be found in our ic package databook (order code 9398 652 90011). re?ow soldering reflow soldering techniques are suitable for all so packages. reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. several techniques exist for reflowing; for example, thermal conduction by heated belt. dwell times vary between 50 and 300 seconds depending on heating method. typical reflow temperatures range from 215 to 250 c. preheating is necessary to dry the paste and evaporate the binding agent. preheating duration: 45 minutes at 45 c. wave soldering wave soldering techniques can be used for all so packages if the following conditions are observed: a double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. the longitudinal axis of the package footprint must be parallel to the solder flow. the package footprint must incorporate solder thieves at the downstream end. during placement and before soldering, the package must be fixed with a droplet of adhesive. the adhesive can be applied by screen printing, pin transfer or syringe dispensing. the package can be soldered after the adhesive is cured. maximum permissible solder temperature is 260 c, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 c within 6 seconds. typical dwell time is 4 seconds at 250 c. a mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. repairing soldered joints fix the component by first soldering two diagonally- opposite end leads. use only a low voltage soldering iron (less than 24 v) applied to the flat part of the lead. contact time must be limited to 10 seconds at up to 300 c. when using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 c.
1995 dec 08 19 philips semiconductors preliminary speci?cation stereo 1fs data input up-sampling ?lter with bitstream continuous dual dac (bcc-dac2) TDA1305t definitions life support applications these products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify philips for any damages resulting from such improper use or sale. data sheet status objective speci?cation this data sheet contains target or goal speci?cations for product development. preliminary speci?cation this data sheet contains preliminary data; supplementary data may be published later. product speci?cation this data sheet contains ?nal product speci?cations. limiting values limiting values given are in accordance with the absolute maximum rating system (iec 134). stress above one or more of the limiting values may cause permanent damage to the device. these are stress ratings only and operation of the device at these or at any other conditions above those given in the characteristics sections of the speci?cation is not implied. exposure to limiting values for extended periods may affect device reliability. application information where application information is given, it is advisory and does not form part of the speci?cation.
philips semiconductors C a worldwide company argentina: ierod, av. juramento 1992 - 14.b, (1428) buenos aires, tel. (541)786 7633, fax. (541)786 9367 australia: 34 waterloo road, north ryde, nsw 2113, tel. (02)805 4455, fax. (02)805 4466 austria: triester str. 64, a-1101 wien, p.o. box 213, tel. (01)60 101-1236, fax. (01)60 101-1211 belgium: postbus 90050, 5600 pb eindhoven, the netherlands, tel. (31)40-2783749, fax. (31)40-2788399 brazil: rua do rocio 220 - 5 th floor, suite 51, cep: 04552-903-s?o paulo-sp, brazil, p.o. box 7383 (01064-970), tel. (011)821-2333, fax. (011)829-1849 canada: philips semiconductors/components: tel. (800) 234-7381, fax. (708) 296-8556 chile: av. santa maria 0760, santiago, tel. (02)773 816, fax. (02)777 6730 china/hong kong: 501 hong kong industrial technology centre, 72 tat chee avenue, kowloon tong, hong kong, tel. (852)2319 7888, fax. (852)2319 7700 colombia: iprelenso ltda, carrera 21 no. 56-17, 77621 bogota, tel. (571)249 7624/(571)217 4609, fax. (571)217 4549 denmark: prags boulevard 80, pb 1919, dk-2300 copenhagen s, tel. (45)32 88 26 36, fax. (45)31 57 19 49 finland: sinikalliontie 3, fin-02630 espoo, tel. (358)0-615 800, fax. (358)0-61580 920 france: 4 rue du port-aux-vins, bp317, 92156 suresnes cedex, tel. (01)4099 6161, fax. (01)4099 6427 germany: p.o. box 10 51 40, 20035 hamburg, tel. (040)23 53 60, fax. (040)23 53 63 00 greece: no. 15, 25th march street, gr 17778 tavros, tel. (01)4894 339/4894 911, fax. (01)4814 240 india: philips india ltd, shivsagar estate, a block, dr. annie besant rd. worli, bombay 400 018 tel. (022)4938 541, fax. (022)4938 722 indonesia: philips house, jalan h.r. rasuna said kav. 3-4, p.o. box 4252, jakarta 12950, tel. (021)5201 122, fax. (021)5205 189 ireland: newstead, clonskeagh, dublin 14, tel. (01)7640 000, fax. (01)7640 200 italy: philips semiconductors s.r.l., piazza iv novembre 3, 20124 milano, tel. (0039)2 6752 2531, fax. (0039)2 6752 2557 japan: philips bldg 13-37, kohnan 2 -chome, minato-ku, tokyo 108, tel. (03)3740 5130, fax. (03)3740 5077 korea: philips house, 260-199 itaewon-dong, yongsan-ku, seoul, tel. (02)709-1412, fax. (02)709-1415 malaysia: no. 76 jalan universiti, 46200 petaling jaya, selangor, tel. (03)750 5214, fax. (03)757 4880 mexico: 5900 gateway east, suite 200, el paso, tx 79905, tel. 9-5(800)234-7381, fax. (708)296-8556 netherlands: postbus 90050, 5600 pb eindhoven, bldg. vb, tel. (040)2783749, fax. (040)2788399 new zealand: 2 wagener place, c.p.o. box 1041, auckland, tel. (09)849-4160, fax. (09)849-7811 norway: box 1, manglerud 0612, oslo, tel. (022)74 8000, fax. (022)74 8341 pakistan: philips electrical industries of pakistan ltd., exchange bldg. st-2/a, block 9, kda scheme 5, clifton, karachi 75600, tel. (021)587 4641-49, fax. (021)577035/5874546 philippines: philips semiconductors philippines inc., 106 valero st. salcedo village, p.o. box 2108 mcc, makati, metro manila, tel. (63) 2 816 6380, fax. (63) 2 817 3474 portugal: philips portuguesa, s.a., rua dr. antnio loureiro borges 5, arquiparque - miraflores, apartado 300, 2795 linda-a-velha, tel. (01)4163160/4163333, fax. (01)4163174/4163366 singapore: lorong 1, toa payoh, singapore 1231, tel. (65)350 2000, fax. (65)251 6500 south africa: s.a. philips pty ltd., 195-215 main road martindale, 2092 johannesburg, p.o. box 7430, johannesburg 2000, tel. (011)470-5911, fax. (011)470-5494 spain: balmes 22, 08007 barcelona, tel. (03)301 6312, fax. (03)301 42 43 sweden: kottbygatan 7, akalla. s-164 85 stockholm, tel. (0)8-632 2000, fax. (0)8-632 2745 switzerland: allmendstrasse 140, ch-8027 zrich, tel. (01)488 2211, fax. (01)481 77 30 taiwan: philips taiwan ltd., 23-30f, 66, chung hsiao west road, sec. 1. taipeh, taiwan roc, p.o. box 22978, taipei 100, tel. (886) 2 382 4443, fax. (886) 2 382 4444 thailand: philips electronics (thailand) ltd., 209/2 sanpavuth-bangna road prakanong, bangkok 10260, thailand, tel. (66) 2 745-4090, fax. (66) 2 398-0793 turkey: talatpasa cad. no. 5, 80640 gltepe/istanbul, tel. (0 212)279 27 70, fax. (0212)282 67 07 ukraine: philips ukraine, 2a akademika koroleva str., office 165, 252148 kiev, tel. 380-44-4760297, fax. 380-44-4766991 united kingdom: philips semiconductors ltd., 276 bath road, hayes, middlesex ub3 5bx, tel. (0181)730-5000, fax. (0181)754-8421 united states: 811 east arques avenue, sunnyvale, ca 94088-3409, tel. (800)234-7381, fax. (708)296-8556 uruguay: coronel mora 433, montevideo, tel. (02)70-4044, fax. (02)92 0601 internet: http://www.semiconductors.philips.com/ps/ for all other countries apply to: philips semiconductors, international marketing and sales, building be-p, p.o. box 218, 5600 md eindhoven, the netherlands, telex 35000 phtcnl, fax. +31-40-2724825 scd47 ? philips electronics n.v. 1995 all rights are reserved. reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. the information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. no liability will be accepted by the publisher for any consequence of its use. publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. printed in the netherlands 513061/50/02/pp20 date of release: 1995 dec 08 document order number: 9397 750 00517

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